BLODGETT GREG A (Total 160 Patents Found)

A circuit and method for preventing glitches from occurring during a termination of a self-refresh mode when a race condition exits between an external row address strobe signal* (RAS*) transitioning to an inactive state and an internally generated self-refresh timing signal transitioning to an inactive state. The circ...
A self compensating clamp circuit and a method which limit the voltage of a pump circuit node to a maximum potential. A first pump circuit provides a first pumped potential at a first node which is greater than a supply potential. The first pumped potential is fed to a second pump circuit which generates a second pumpe...
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit...
A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3...
A memory device includes an output buffer for temporarily storing first and second data that are sequentially retrieved from a memory array during a read cycle. The output buffer holds the first data until it is replaced by the second data. A pulse circuit is connected to the memory array and output buffer, and is desi...
在DRAM自动刷新期间禁止用于指令和地址信号(106)的输入缓冲器(102)的功率节省电路(100)。在自动刷新结束时以不引起产生伪指令的方式重新使能输入缓冲器(102)。功率节省电路通过在用于指令信号的输入缓冲器禁止时将内部指令信号(116)偏置到“...
A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal comma...
A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3...
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a...
A charge pump circuit and method for increasing a value of a supply potential. The charge pump circuit features a first stage circuit for generating an intermediate pumped potential greater than an input supply potential. The intermediate pumped potential becomes a supply potential for a portion of a second stage circu...
A method and circuit for generating a self-refresh mode signal and a self-refresh cycle signal. The circuit is a dynamic random access memory (DRAM) device having a control array of control cells charged to a potential by a current source and having a monitor circuit for monitoring the potential of the control array. T...
A power saving circuit (100) disables input buffers (102) for command and address signals (106) during an auto-refresh of a DRAM. The input buffers (102) are re-enabled at the end of the auto-refreshin a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by...
An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word...