Semiconductor memory device having an improved error correction capability

Abstract

A semiconductor memory device which is comprised of a plurality m of electrically isolated data memory sub-arrays for storing data bits and a plurality k of electrically isolated parity memory sub-arrays for storing parity bits, wherein each of the data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line. Row address decoders function to activate a selected word line in each of the memory sub-arrays, and column address decoders, in combination with column selection circuitry, function to couple a selected bit line in each of the memory sub-arrays to a plurality m of sense amplifiers, which function to sense the voltage level of respective ones of the selected bit lines, and produce output data and parity bits representative of these sensed voltage levels. An error checking and correction circuit compares the output data and parity bits in order to detect and correct errors in the output data bits. Because of the unique architecture of the semiconductor memory device of this invention, defects in word lines or bit lines are confined to a single bit, thereby rendering these defects easily reparable by means of an ECC circuit alone, and thus dispensing with the need for a redundant memory circuit.

Claims

What is claimed is: 1. A semiconductor memory device, comprising: a plurality m of electrically isolated data memory sub-arrays for storing data bits; a plurality k of electrically isolated parity memory sub-arrays for storing parity bits; wherein each of said data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line; row decoding means for selecting a word line in each of said data and parity memory sub-arrays; column decoding means for selecting a bit line in each of said data and parity memory sub-arrays; a plurality of sense amplifiers for sensing the voltage level of respective ones of said selected bit lines, and for producing output data and parity bits representative of the sensed voltage levels of said selected bit lines; and, an error checking and correction circuit for detecting and correcting errors in said output data bits. 2. The semiconductor memory device as set forth in claim 1, wherein said error checking and correction circuit includes circuitry for comparing said output data bits and said output parity bits. 3. The semiconductor memory device as set forth in claim 1, wherein said data and parity memory sub-arrays are electrically isolated from each other. 4. The semiconductor memory device as set forth in claim 3, wherein said row decoding means includes a plurality, (m+k)/2, of row decoders disposed between respective adjacent pairs of said data and parity memory sub-arrays. 5. The semiconductor memory device as set forth in claim 4, wherein each of said row decoders includes a first driver circuit for activating a selected word line in a first memory sub-array of the respective adjacent pair and a second driver circuit for activating a selected word line in a second memory sub-array of the respective adjacent pair, said first and second driver circuits being electrically isolated from each other. 6. The semiconductor memory device as set forth in claim 5, wherein each column of each of said data and parity memory sub-arrays includes at least two strings of memory cells and means for selectively coupling a selected one of said strings to said common bit line associated with said column. 7. The semiconductor memory device as set forth in claim 6, wherein each of said selectively coupling means includes at least two string selection lines selectively activated by a respective one of said row decoders. 8. The semiconductor memory device as set forth in claim 7, wherein said word lines and said string selection lines for each of said data and parity memory sub-arrays are electrically isolated from one another. 9. The semiconductor memory device as set forth in claim 8, wherein the number m of data memory sub-arrays and the number k of parity memory sub-arrays are selected in accordance with the Hamming code. 10. The semiconductor memory device as set forth in claim 9, wherein the semiconductor memory device is a read-only type of memory device. 11. The semiconductor memory device as set forth in claim 9, wherein the semiconductor memory device is a random-access type of memory device. 12. The semiconductor memory device as set forth in claim 11, wherein the semiconductor memory device is a DRAM fabricated on a single semiconductor chip. 13. A semiconductor memory device, comprising: a plurality m of electrically isolated data memory sub-arrays for storing data bits; a plurality k of electrically isolated parity memory sub-arrays for storing parity bits; wherein each of said data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line; a plurality x of row decoders for selecting a word line in each of said data and parity memory sub-arrays; a column selector for selecting a bit line in each of said data and parity memory sub-arrays; a plurality of sense amplifiers for sensing the voltage level of respective ones of said selected bit lines, and for producing output data and parity bits representative of the sensed voltage levels of said selected bit lines; and, an error checking and correction circuit responsive to said output data and parity bits for detecting and correcting errors in said output data bits. 14. The semiconductor memory device as set forth in claim 13, wherein x=(m+k)/2. 15. The semiconductor memory device as set forth in claim 14, wherein said plurality of row decoders are disposed between respective adjacent pairs of said data and parity memory sub-arrays. 16. The semiconductor memory device as set forth in claim 13, wherein said data and parity memory sub-arrays are electrically isolated from each other. 17. The semiconductor memory device as set forth in claim 15, wherein each of said row decoders includes a first driver circuit for activating a selected word line in a first memory sub-array of the respective adjacent pair and a second driver circuit for activating a selected word line in a second memory sub-array of the respective adjacent pair, said first and second driver circuits being electrically isolated from each other. 18. The semiconductor memory device as set forth in claim 17, wherein each column of each of said data and parity memory sub-arrays includes at least two strings of memory cells and means for selectively coupling a selected one of said strings to said common bit line associated with said column. 19. The semiconductor memory device as set forth in claim 18, wherein each of said selectively coupling means includes at least two string selection lines selectively activated by a respective one of said row decoders. 20. The semiconductor memory device as set forth in claim 19, wherein said word lines and said string selection lines for each of said data and parity memory sub-arrays are electrically isolated from one another.
BACKGROUND OF THE INVENTION The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device having an improved architecture which isolates bit line and word line defects to a single bit, to thereby facilitate improved error correction capability relative to semiconductor memory devices having a conventional architecture. In the field of semiconductor memory devices, it is conventional to repair defects of the memory cells thereof by means of either a redundant memory circuit or an ECC circuit, to thereby improve the yield of the process for manufacturing the semiconductor memory devices. However, these conventional techniques for repairing defective memory cells suffer from the following drawbacks and shortcomings. Namely, in semiconductor memory devices which utilize a redundant memory circuit, after the wafer fabrication process, an additional procedure is required to identify the defective memory cells and to program the redundant memory circuit with the addresses of the identified defective memory cells. This is a time-consuming procedure which reduces throughput and increases manufacturing costs. Further, it is difficult to utilize the redundancy technique in read only memories (ROMs) and the like. In semiconductor memory devices which utilize an ECC circuit, the device architecture limits the effectiveness of the ECC circuit, in a manner which will become clear hereinafter. In general, the ECC circuit requires k parity bits for each m-bit input data word, in accordance with the well-known Hamming code, which is mathematically represented by the following equation (1): (1) 2 k ≧m+k+1, where m is the number of data bits per data word, and k is the corresponding number of parity bits. For example, if the number (m) of data bits is 8, the number (k) of parity bits is 4, and if the number (m) of data bits is 16, the number (k) of parity bits is 5. During a write mode of operation, the ECC circuit generates k parity bits corresponding to the m data bits of an input data word, and both the m data bits and the corresponding k parity bits are stored in the memory cell array of the memory device. During a read mode of operation, the m data bits and the corresponding k parity bits of an output data word are read-out of the memory cell array, and the ECC circuit compares the k parity bits and the m data bits to detect and correct errors which may be present in the output data word. With reference now to FIGS. 1, 2, and 3, there can be seen a semiconductor memory device incorporating an ECC circuit having a conventional architecture, and disclosed in U.S. Pat. No. 4,692,923, issued to Alan D. Poeppelman on Sep. 6, 1987. The semiconductor memory device illustrated in FIG. 1 includes a plurality of memory sub-arrays D0-DN, the interconnection of which is depicted in greater detail in FIG. 2. FIG. 3 is a more detailed circuit diagram of the portions of the memory device depicted in FIG. 2. As can be readily seen in FIGS. 1 and 2, each of the memory sub-arrays DO-DN includes a plurality of stack sets Ni (i=1-N), each comprised of two strings of memory cells. With particular reference now to FIGS. 1 and 3, there can be seen a plurality of bank select lines each of which are connected to a different stack set in each of the memory sub-arrays DO-DN. It will be appreciated that, in operation, the activation of a particular bank select line will result in the selection of a different stack set in each of the memory sub-arrays DO-DN, i.e., a bank of different stack sets, one from each sub-array. For example, the activation of the bank select line N selects stack set 0 in the sub-array DO, the stack set 1 in the sub-array D1, and the stack set N in the sub-array DN. With this configuration, defects in a particular word line can be confined to only one bit of the output data word, since each bit of the output data word is taken from a stack set which contains different word lines than do the stack sets from which the remaining bits of the output data word are taken. However, the above-described ECC scheme suffers from the following drawbacks and shortcomings. Namely, defects in the bank select lines themselves can not be repaired at all, thereby limiting the utility of this ECC scheme. Further, since each bank select line is connected to selection transistors in all of the sub-arrays, the loading of the bank select lines is undesirably large, thereby increasing power dissipation and causing operational delays. Moreover, since the bank select lines must cross the memory sub-arrays, the layout and maskwork of the memory chip are rendered more difficult, thereby unduly increasing the cost and complexity of fabricating the memory chips, and unduly decreasing the reliability thereof. Furthermore, operating speed is undesirably decreased and power consumption undesirably increased by virtue of the architecture of the conventional semiconductor memory device, as will now be described with particular reference to FIG. 3. More particularly, a bus row signal O of an even row bus line is connected to word lines WL31, WL32 through respective depletion-type MOS transistors whose gates are connected to a supply voltage Vcc, and a bus row signal 1 of an odd row bus line is connected to word lines WL41, WL42 through respective depletion-type MOS transistors whose gates connected are to the supply voltage Vcc. With this arrangement, all of the word lines are simultaneously changed to either the supply voltage Vcc or the ground voltage Vss when the voltage level of the bus row signal 0 or the bus row signal 1 is changed, thereby resulting in an unduly high level of power consumption and decreased operating speed. In a high integration density memory device, e.g., a 64M or 256M DRAM, this problem is magnified, since the number of word lines connected to the bus row signals is significantly greater than is the case with presently available DRAMs. Based upon the above and foregoing, ot can be appreciated that there presently exists a need in the semiconductor memory art for a semiconductor memory device which eliminates the above-described drawbacks and shortcomings of the presently available semiconductor memory devices. The present invention fulfills this need. SUMMARY OF THE INVENTION The present invention encompasses a semiconductor memory device which is comprised of a plurality m of electrically isolated data memory sub-arrays for storing data bits and a plurality k of electrically isolated parity memory sub-arrays for storing parity bits, wherein each of the data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line. Row address decoders function to activate a selected word line in each of the memory sub-arrays, and column address decoders, in combination with column selection circuitry, function to couple a selected bit line in each of the memory sub-arrays to a plurality m of sense amplifiers, which function to sense the voltage level of respective ones of the selected bit lines, and produce output data and parity bits representative of these sensed voltage levels. An error checking and correction circuit compares the output data and parity bits in order to detect and correct errors in the output data bits. The plurality of row decoders are preferably disposed between respective adjacent pairs of the data and parity memory sub-arrays. Each of the row decoders preferably includes a first drive circuit for activating a selected word line in a first memory sub-array of the respective adjacent pair and a second driver circuit for activating a selected word line in a second memory sub-array of the respective adjacent pair, with the first and second driver circuits being electrically isolated from each other. Because of the unique architecture of the semiconductor memory device of this invention, defects in word lines or bit lines are confined to a single bit, thereby rendering these defects easily reparable by means of an ECC circuit alone, and thus dispensing with the need for a redundant memory circuit. BRIEF DESCRIPTION OF THE DRAWINGS These and various other features and advantages of the present invention will be readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and, in which: FIG. 1 is a block diagram of a conventional semiconductor memory device disclosed in U.S. Pat. No. 4,692,923; FIG. 2 is a more detailed block diagram of two of the subarrays (D0 and D1) of the semiconductor memory device depicted in FIG. 1; FIG. 3 is a circuit diagram of the two subarrays depicted in FIG. 2; FIG. 4 is a block diagram of a semiconductor memory device constructed in accordance with a first preferred embodiment of the present invention; FIG. 5 is a circuit diagram of two of the subarrays (D0 and D1) of the semiconductor memory device depicted in FIG. 4; FIG. 6 is a circuit diagram of an exemplary embodiment of a row decoder which has a particular utility in the semiconductor memory device depicted in FIG. 4; and, FIG. 7 is a block diagram of a semiconductor memory device constructed in accordance with a second preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION With reference now to FIG. 4, a semiconductor memory device constructed in accordance with a first preferred embodiment of the present invention will now be described. The semiconductor memory device of this embodiment includes a memory cell array comprised of twelve memory blocks or sub-arrays D0-D7, and P0-P3. The memory sub-arrays D0-D7 and P0-P3 each include a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row (i) connected to a common word line (W/Li), and the memory cells in each column (j) connected to a common bit line (B/Lj). The memory sub-arrays D0-D7 are adapted to store data bits, and the memory sub-arrays P0-P3 are adapted to store parity bits, which are utilized by an ECC circuit to correct detected defects in the corresponding data bits. As will be readily evident to those skilled in the semiconductor memory art, in this embodiment, there are four parity bits for each eight-bit data word. The data bit sub-arrays D0-D7 and the parity bit sub-arrays P0-P3 can suitably be randomly arranged, although this is not limiting to the present invention, as any other convenient arrangement may be employed. With continuing reference to FIG. 4, row and column address buffers 42,45 amplify externally supplied row address signals and column address signals for application to the row predecoders 43, and the column predecoder 46, respectively. With additional reference now to FIG. 5, the row predecoders 43 and row decoders 51 function to decode the row address signals, and to select one word line (W/Li) out of a plurality of word lines (WLO-WLn), and one string selection line (SSLi) out of a plurality of string selection lines (SSLO-SSLn), in each of the memory sub-arrays D0-D7 and P0-P3). Although not limiting to the present invention, the row decoders are preferably implemented like the one depicted in FIG. 6, which is disclosed in Korea Patent No. 1989-16428, filed Nov. 13, 1989, entitled "Word Line Decoder of a Semiconductor Memory Device", and assigned to the assignee of the present invention. An improved word line decoder which also has particular utility in the practice of the present invention is the one disclosed in Korea Patent No. 1992-20209, filed Oct. 30, 1992, and also assigned to the assignee of the present invention. The column predecoder 46 and the column selectors 47 function to decode the column address signals, and to select one bit line (B/L) out of a plurality of bit lines in each of the memory sub-arrays D0-D7 and P0-P3. Twelve sense amplifiers (shown in box 48) selectively coupled to respective ones of the the twelve selected bit lines function to sense the eight data bits and four parity bits read from the selected one of the memory cells in each respective one of the twelve memory sub-arrays, by sensing the voltage on the respective selected bit lines. The ECC circuit (shown in box 48) uses the four sensed parity bits to detect errors, preferably of not more than one bit, in the eight data bits, and corrects any error so detected. The ECC circuit applies the eight data bits, corrected as required, to a data output buffer 49, which serves to amplify the eight corrected data bits for application to external circuitry. With continuing reference to FIG. 5, the internal operation of the memory device will now be described in greater detail. More particularly, during a read operation as described above, one string selection line SSLi is selected in each memory sub-array by a driver of the row decoder coupled thereto, and further, one word line WLi is selected in each selected string in each memory sub-array by a driver of the row decoder coupled thereto. In this manner, only one memory cell is selected in each memory sub-array, corresponding to one data or parity bit of the twelve-bit output data word. In accordance with the present invention, the drivers of one row decoder are electrically isolated from the drivers of the other row decoders, and further, each pair of memory sub-arrays (e.g., D0 and D1) coupled to a common row decoder, are connected to different, electrically isolated drivers of the common row decoder. Further, the string selection lines and word lines are electrically isolated from each other. With this novel architecture, even if one of the string selection lines or one of the word lines are shorted, or otherwise defective, the defect would be isolated to only one memory cell, and therefore, only one of the twelve data and parity bits comprising each word read from the entire memory cell array would be defective, which can be easily corrected by the ECC circuit. Further, since only one memory cell in one memory sub-array is selected by one string line and one word line signal, the loading of these lines is relatively small, thus facilitating a higher speed of operation and lower power dissipation than is possible with semiconductor memory devices having a conventional architecture. Moreover, this loading is not increased with increases in the density of the semiconductor memory device. With reference now to FIG. 7, there can be seen a semiconductor memory device constructed in accordance with a second preferred embodiment of the present invention, and having the same architecture as that of the memory device of the first preferred embodiment, except that the memory cell array is comprised of sixteen memory sub-arrays D0-D15 for storing data bits, and five memory sub-arrays P0-P4 for storing parity bits. In general, the number of normal/data and parity bits utilized is not limiting to the present invention. As can be appreciated from the foregoing description, defects in bit lines or word lines of a semiconductor memory device constructed in accordance with the principles of the present invention are confined to a single bit by means of independently activating n electrically isolated string selection lines and word lines by means of n/2 row decoders, thereby enabling any such defects to be repaired by an ECC circuit alone. Since all defects are reparable by the ECC circuit alone, the need for a redundant memory circuit is eliminated, thereby eliminating the drawbacks and shortcomings of semiconductor memory chips which utilize redundant memory, e.g., increased chip size, decreased throughput, increased manufacturing costs, decreased yield, and decreased reliability. Moreover, the semiconductor memory device embodying the present invention exhibits enhanced performance relative to the presently available semiconductor memory devices which utilize an ECC circuit for repairing defects, e.g., lower power consumption and increased operating speed. Although two preferred embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the pertinent art will still fall within the spirit and scope of the present invention as defined in the appended claims.

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (1)

    Publication numberPublication dateAssigneeTitle
    US-4692923-ASeptember 08, 1987Ncr CorporationFault tolerant memory

NO-Patent Citations (0)

    Title

Cited By (121)

    Publication numberPublication dateAssigneeTitle
    US-2005044459-A1February 24, 2005Scheuerlein Roy E., Johnson Mark G., Bosch Derek J., Alper Ilkbahar, Tringali J. JamesRedundant memory structure using bad bit pointers
    US-8601341-B2December 03, 2013Micron Technologies, Inc.Memory system and method using ECC with flag bit to identify modified data
    US-6820185-B2November 16, 2004Matrix Semiconductor, Inc.Method for identifying memory cells storing replacement data on a memory device
    US-6539504-B1March 25, 2003Siemens AktiengesellschaftMemory system having error monitoring apparatus for multi-bit errors
    US-2006069856-A1March 30, 2006Klein Dean AMemory controller method and system compensating for memory cell data losses
    US-2008212352-A1September 04, 2008Samsung Electronics Co., Ltd.Multi-layer semiconductor memory device comprising error checking and correction (ecc) engine and related ecc method
    US-6535452-B2March 18, 2003Fujitsu LimitedSemiconductor memory device having error correction function for data reading during refresh operation
    US-2004206982-A1October 21, 2004Lee Thomas H., Johnson Mark G.Three-dimensional memory device with ECC circuitry
    US-6901549-B2May 31, 2005Matrix Semiconductor, Inc.Method for altering a word stored in a write-once memory device
    US-8504903-B2August 06, 2013SK Hynix Inc.Data error check circuit, data error check method, data transmission method using data error check function, semiconductor memory apparatus and memory system using data error check function
    US-7134069-B1November 07, 2006Madrone Solutions, Inc.Method and apparatus for error detection and correction
    US-6694415-B2February 17, 2004Matrix Semiconductor, Inc.Methods for permanently preventing modification of a partition or file
    US-7340668-B2March 04, 2008Micron Technology, Inc.Low power cost-effective ECC memory system and method
    US-6687860-B1February 03, 2004Matsushita Electric Industrial Co., Ltd.Data transfer device and data transfer method
    US-7526713-B2April 28, 2009Micron Technology, Inc.Low power cost-effective ECC memory system and method
    US-2013077419-A1March 28, 2013Kabushiki Kaisha ToshibaData generation apparatus
    US-7447973-B2November 04, 2008Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-6697928-B2February 24, 2004Matrix Semiconductor, Inc.System and method for storing first and second files in a memory device
    US-2006056259-A1March 16, 2006Klein Dean AMemory controller method and system compensating for memory cell data losses
    US-7840876-B2November 23, 2010Qimonda AgPower savings for memory with error correction mode
    US-2008285365-A1November 20, 2008Bosch Derek J, Moore Christopher SMemory device for repairing a neighborhood of rows in a memory array using a patch table
    US-7116602-B2October 03, 2006Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-7184352-B2February 27, 2007Micron Technology, Inc.Memory system and method using ECC to achieve low power refresh
    US-2010083065-A1April 01, 2010Madrone Solutions, Inc.Method and apparatus for error detection and correction
    US-2006152989-A1July 13, 2006Klein Dean AMethod and system for controlling refresh to avoid memory cell data losses
    US-9384092-B2July 05, 2016Samsung Electronics Co., Ltd.Semiconductor memory device with multiple sub-memory cell arrays and memory system including same
    US-5469450-ANovember 21, 1995Samsung Electronics Co., Ltd.Nonvolatile memory device including multi-ECC circuit
    US-2006013052-A1January 19, 2006Klein Dean AMethod and system for controlling refresh to avoid memory cell data losses
    US-2005289444-A1December 29, 2005Klein Dean ALow power cost-effective ECC memory system and method
    US-7958390-B2June 07, 2011Sandisk CorporationMemory device for repairing a neighborhood of rows in a memory array using a patch table
    US-6591394-B2July 08, 2003Matrix Semiconductor, Inc.Three-dimensional memory array and method for storing data bits and ECC bits therein
    US-7623392-B2November 24, 2009Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-8446783-B2May 21, 2013Micron Technology, Inc.Digit line comparison circuits
    US-2006044913-A1March 02, 2006Klein Dean A, John SchreckMemory system and method using ECC to achieve low power refresh
    US-7203084-B2April 10, 2007Sandisk 3D LlcThree-dimensional memory device with ECC circuitry
    US-7836374-B2November 16, 2010Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-9286161-B2March 15, 2016Micron Technology, Inc.Memory system and method using partial ECC to achieve low power refresh and fast access to data
    US-2005249010-A1November 10, 2005Klein Dean AMemory controller method and system compensating for memory cell data losses
    US-7545689-B2June 09, 2009Sandisk 3D LlcMethod and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
    US-7212454-B2May 01, 2007Sandisk 3D LlcMethod and apparatus for programming a memory array
    US-5680362-AOctober 21, 1997United Memories, Inc., Nippon Steel Semiconductor CorporationCircuit and method for accessing memory cells of a memory device
    US-2008092016-A1April 17, 2008Micron Technology, Inc.Memory system and method using partial ECC to achieve low power refresh and fast access to data
    US-7603592-B2October 13, 2009Hitachi, Ltd., Elpida Memory, Inc.Semiconductor device having a sense amplifier array with adjacent ECC
    US-2006206769-A1September 14, 2006Klein Dean AMemory system and method having selective ECC during low power refresh
    US-8832522-B2September 09, 2014Micron Technology, Inc.Memory system and method using partial ECC to achieve low power refresh and fast access to data
    US-7779341-B2August 17, 2010Samsung Electronics Co., Ltd.NAND flash memory device performing error detecting and data reloading operation during copy back program operation
    US-6233717-B1May 15, 2001Samsung Electronics Co., Ltd.Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein
    US-9703632-B2July 11, 2017Nxp B. V.Sleep mode operation for volatile memory circuits
    US-6996017-B2February 07, 2006Matrix Semiconductor, Inc.Redundant memory structure using bad bit pointers
    US-8880974-B2November 04, 2014Micron Technology, Inc.Memory system and method using ECC with flag bit to identify modified data
    US-7277336-B2October 02, 2007Sandisk 3D LlcMethod and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
    US-2004190357-A1September 30, 2004Scheuerlein Roy E., Johnson Mark G., Bosch Derek J., Alper Ilkbahar, Tringali J. JamesRedundant memory structure using bad bit pointers
    US-7428687-B2September 23, 2008Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-2008109705-A1May 08, 2008Pawlowski J Thomas, John SchreckMemory system and method using ECC with flag bit to identify modified data
    US-2008201626-A1August 21, 2008Qimonda North America Corp.Power savings for memory with error correction mode
    US-2007170268-A1July 26, 2007Samsung Electronics Co., Ltd.Memory cards, nonvolatile memories and methods for copy-back operations thereof
    US-2006265636-A1November 23, 2006Klaus HummlerOptimized testing of on-chip error correction circuit
    US-8006164-B2August 23, 2011Intel CorporationMemory cell supply voltage control based on error detection
    US-2011138251-A1June 09, 2011Pawlowski J ThomasMemory system and method using partial ecc to achieve low power refresh and fast access to data
    US-7277345-B2October 02, 2007Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-7225390-B2May 29, 2007Elpida Memory, Inc.Semiconductor memory device provided with error correcting code circuitry
    US-2006158950-A1July 20, 2006Klein Dean AMethod and system for controlling refresh to avoid memory cell data losses
    US-2007038919-A1February 15, 2007Hitachi, Ltd., Elpida Memory, Inc.Semiconductor memory device
    US-7966518-B2June 21, 2011Sandisk CorporationMethod for repairing a neighborhood of rows in a memory array using a patch table
    US-2008082899-A1April 03, 2008Intel CorporationMemory cell supply voltage control based on error detection
    US-2006010339-A1January 12, 2006Klein Dean AMemory system and method having selective ECC during low power refresh
    US-7894289-B2February 22, 2011Micron Technology, Inc.Memory system and method using partial ECC to achieve low power refresh and fast access to data
    US-7898892-B2March 01, 2011Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-2003115535-A1June 19, 2003March Roger W., Moore Christopher S., Johnson Mark G.Method for altering a word stored in a write-once memory device
    US-8937844-B2January 20, 2015Kabushiki Kaisha ToshibaApparatus for generating write data and readout data
    US-2006056260-A1March 16, 2006Klein Dean AMemory controller method and system compensating for memory cell data losses
    US-2008170440-A1July 17, 2008Samsung Electronics Co., Ltd.Flash memory device with split string selection line structure
    US-5784391-AJuly 21, 1998International Business Machines CorporationDistributed memory system with ECC and method of operation
    US-7280386-B2October 09, 2007Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-2006140026-A1June 29, 2006Alper Ilkbahar, Bosch Derek JMethod and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
    US-2007291563-A1December 20, 2007Alper Ilkbahar, Bosch Derek JMethod and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
    US-6651133-B2November 18, 2003Matrix Semiconductor, Inc.Method and data storage device for writing a minimum number of memory cells in a memory device
    US-8136017-B2March 13, 2012Samsung Electronics Co., Ltd.Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method
    US-7558142-B2July 07, 2009Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-2010054070-A1March 04, 2010Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-6965537-B1November 15, 2005Micron Technology, Inc.Memory system and method using ECC to achieve low power refresh
    US-5577004-ANovember 19, 1996Emc CorporationMemory system and method
    US-2007079218-A1April 05, 2007Takeshi Nagai, Shinji MiyanoSemiconductor memory device having data holding mode using ECC function
    US-6647471-B2November 11, 2003Matrix Semiconductor, Inc.Methods for overwriting data in a memory device
    US-6633509-B2October 14, 2003Matrix Semiconductor, Inc.Partial selection of passive element memory cell sub-arrays for write operations
    US-2006050567-A1March 09, 2006Xilinx, Inc.Using transfer bits during data transfer from non-volatile to volatile memories
    US-8667367-B2March 04, 2014Intel CorporationMemory cell supply voltage control based on error detection
    US-8413007-B2April 02, 2013Micron Technology, Inc.Memory system and method using ECC with flag bit to identify modified data
    US-7447974-B2November 04, 2008Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-5841961-ANovember 24, 1998Mitsubishi Denki Kabushiki KaishaSemiconductor memory device including a tag memory
    US-6868022-B2March 15, 2005Matrix Semiconductor, Inc.Redundant memory structure using bad bit pointers
    US-2007067705-A1March 22, 2007Hyung-Gon KimNAND flash memory device performing error detecting and data reloading operation during copy back program operation
    US-7817473-B2October 19, 2010Samsung Electronics Co., Ltd.Flash memory device with split string selection line structure
    US-6661730-B1December 09, 2003Matrix Semiconductor, Inc.Partial selection of passive element memory cell sub-arrays for write operation
    US-6738883-B2May 18, 2004Matrix Semiconductor, Inc.Memory devices and methods for use therewith
    US-8279683-B2October 02, 2012Micron Technology, Inc.Digit line comparison circuits
    US-8359517-B2January 22, 2013Micron Technology, Inc.Memory system and method using partial ECC to achieve low power refresh and fast access to data
    US-7644348-B2January 05, 2010Madrone Solutions, Inc.Method and apparatus for error detection and correction
    US-7099221-B2August 29, 2006Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-2006291303-A1December 28, 2006Bendik Kleveland, Lee Tae H, Yu Seung G, Chia Yang, Feng Li, Xiaoyu YangMethod and apparatus for programming a memory array
    US-2015006994-A1January 01, 2015Samsung Electronics Co., Ltd.Semiconductor memory device with multiple sub-memory cell arrays and memory system including same
    US-9064600-B2June 23, 2015Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-2003115514-A1June 19, 2003Alper Ilkbahar, Scheuerlein Roy E., Bosch Derek J.Memory device and method for storing bits in non-adjacent storage locations in a memory array
    US-6981091-B2December 27, 2005Xilinx,Inc.Using transfer bits during data transfer from non-volatile to volatile memories
    US-2008288813-A1November 20, 2008Bosch Derek J, Moore Christopher SMethod for repairing a neighborhood of rows in a memory array using a patch table
    US-2007214403-A1September 13, 2007Madrone Solutions, Inc.Method and apparatus for error detection and correction
    US-7818651-B2October 19, 2010Kabushiki Kaisha ToshibaSemiconductor memory device having data holding mode using ECC function
    US-6925545-B2August 02, 2005Matrix Semiconductor, Inc.Configuring file structures and file system structures in a memory device
    US-2008002503-A1January 03, 2008Klein Dean AMethod and system for controlling refresh to avoid memory cell data losses
    US-2004008562-A1January 15, 2004Elpida Memory, IncSemiconductor memory device
    US-7219271-B2May 15, 2007Sandisk 3D LlcMemory device and method for redundancy/self-repair
    US-7127552-B2October 24, 2006Xilinx, Inc.Using transfer bits during data transfer from non-volatile to volatile memories
    US-7272066-B2September 18, 2007Micron Technology, Inc.Method and system for controlling refresh to avoid memory cell data losses
    US-2009024884-A1January 22, 2009Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-2004177229-A1September 09, 2004Matrix Semiconductor, Inc.Configuring file structures and file system structures in a memory device
    US-7461320-B2December 02, 2008Micron Technology, Inc.Memory system and method having selective ECC during low power refresh
    US-2003084230-A1May 01, 2003Xilinx, Inc.Using transfer bits during data transfer from non-volatile to volatile memories
    US-7900120-B2March 01, 2011Micron Technology, Inc.Memory system and method using ECC with flag bit to identify modified data
    US-6928590-B2August 09, 2005Matrix Semiconductor, Inc.Memory device and method for storing bits in non-adjacent storage locations in a memory array
    US-8689077-B2April 01, 2014Micron Technology, Inc.Memory controller method and system compensating for memory cell data losses
    US-2003115518-A1June 19, 2003Bendik Kleveland, Alper Ilkbahar, Scheuerlein Roy E.Memory device and method for redundancy/self-repair